There are many designs and architectures for CPUs integrated onto a silicon chip, where the CPU may represent the majority of the silicon area or just some fraction of it, and where the CPU executes instructions which are stored in on-chip or off-chip memory. Typically such a CPU contains a register which acts as the pointer to, or memory address of, an instruction for execution which may be known variously as Instruction Pointer (Iptr), Program Counter (PC) and others. There may be several registers containing various versions of the Instruction Pointer such as: the pointer to the instruction currently executing, the pointer to the next instruction to be executed, the pointer to the next instruction to be fetched from memory, etc.
According to the various possible architectures, the task of fetching instructions from memory may be performed by a distinguishable instruction fetch unit. Further variations include letting such an instruction fetch unit access memory independent from normal CPU data accesses, inserting a cache, or inserting separate instruction and data caches between the CPU and main memory.
Knowledge of the value of the Instruction Pointer register is of particular importance when performing diagnostic functions on software which is running on a CPU. In the simplest case, the value of the Instruction Pointer can be deduced by observing the memory address value on an external memory bus. In more complex examples however, the value of the Iptr is hidden within the depths of the CPU.
Another important feature for software diagnostics is the ability to stop the CPU, or take some other action, when it reaches a particular instruction. This is commonly known as breakpointing. When the Iptr can be deduced from external pins, then breakpointing can be assisted by external hardware. When this is not possible, there are two schemes commonly employed to achieve breakpointing.
According to one scheme, "software breakpointing" is implemented by modifying the memory at the location of the instruction to be breakpointed to replace it with an instruction which the CPU executes in place of the breakpointed instruction and which achieves the desired effect such as stopping. However, this solution is intrusive, it does not work when the instructions are stored in read-only memory, and requires a significant overhead to replace the correct instruction when the user wishes to proceed after a breakpoint.
According to a second scheme one or more registers and comparison logic are added, where each such a register contains the breakpoint value. When the Iptr matches one of the breakpoint register values the CPU is stopped. This solution needs the hardware present in or very closely associated with the CPU and so it cannot easily be removed for production versions. It needs a mechanism for loading any breakpoint registers which is either intrusive if this has to be done via the CPU itself or requires other hardware support such as additional external pins. The situation is complicated when instructions can be fetched but not executed because of an interrupt at the same instance as the CPU was about to execute the breakpointed instruction. Furthermore such a mechanism can only work successfully if the CPU can stop safely at the breakpointed instruction.
It is an object of the present invention to provide an improved breakpointing system.